The present disclosure generally relates to computer systems, and more specifically, to cache prefetching.
A microprocessor in a computer system may employ a concept known as micro partition prefetch (MPP). Micro partition prefetch provides a mechanism for hardware to write L2 or L3 cache address tags to a memory buffer. In particular, the addresses of recently used cache lines by a virtual processor are saved to the memory buffer. The addresses are recorded while the virtual processor is dispatched. The virtual processor is then undispatched, and the addresses have been stored in the memory buffer. Then, when the virtual processor is redispatched at a later point in time, the cache lines associated with the addresses saved in the memory buffer are prefetched and stored in the cache. It is assumed that some percentage of the recently used addresses will be used again by the virtual processor, so fetching these addresses into cache should improve overall performance.
However, micro partition prefetch may hinder system performance in some implementations. First, the previously saved cache state may include items that will not be used when the virtual processor is redispatched. Prefetching these items eliminates potential cache hits that might occur for this or another virtual processor. Second, micro partition prefetch increases memory subsystem traffic, which could result in delays for accesses that occur on other processors on the same chip.